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Visar resultat 21 - 25 av 110 avhandlingar som matchar ovanstående sökkriterier.
21. High Performance Hybrid Memory Systems with 3D-stacked DRAM
Sammanfattning : The bandwidth of traditional DRAM is pin limited and so does not scale well with the increasing demand of data intensive workloads limiting performance. 3D-stacked DRAM can alleviate this problem providing substantially higher bandwidth to a processor chip. LÄS MER
22. Data Prefetching Techniques Targeting Single and a Network of Processing Nodes
Sammanfattning : This thesis considers two approaches to the design of high-performance computers. In a single processing node with one processor, performance is degraded when requested data is not found in the cache, because it has to be retrieved from slower memory. LÄS MER
23. Exploiting data locality in adaptive architectures
Sammanfattning : The speed of processors increases much faster than the memory access time. This makes memory accesses expensive. To meet this problem, cache hierarchies are introduced to serve the processor with data. However, the effectiveness of caches depends on the amount of locality in the application's memory access pattern. LÄS MER
24. Design Considerations of Value-aware Caches
Sammanfattning : On-chip cache memories are instrumental in tackling several performance and energy issues facing contemporary and future microprocessor chip architectures. First, they are key to bridge the growing speed-gap between memory and processors. LÄS MER
25. Adaptive Resource Management Techniques for High Performance Multi-Core Architectures
Sammanfattning : Reducing the average memory access time is crucial for improving the performance of applications executing on multi-core architectures. With workload consolidation this becomes increasingly challenging due to shared resource contention. Previous works has proposed techniques for partitioning of shared resources (e.g. LÄS MER