Vertical III-V Nanowires For In-Memory Computing

Sammanfattning: In recent times, deep neural networks (DNNs) have demonstrated great potential in various machine learning applications,such as image classification and object detection for autonomous driving. However, increasing the accuracy of DNNsrequires scaled, faster, and more energy-efficient hardware, which is limited by the von Neumann architecture whereseparate memory and computing units lead to a bottleneck in performance. A promising solution to address the vonNeumann bottleneck is in-memory computing, which can be achieved by integrating non-volatile memory cells such asRRAMs into dense crossbar arrays. On the hardware side, the 1-transistor-1-resistor (1T1R) configuration has been centralto numerous demonstrations of reservoir, in-memory and neuromorphic computing.In this thesis, to achieve a 1T1R cell with a minimal footprint of 4F2, a technology platform has been developed to integrate avertical nanowire GAA MOSFET as a selector device for the RRAM. Firstly, the effect of the geometry (planar to vertical) ofthe ITO/HfO2/TiN RRAM cell was studied where low energy switching (0.49 pJ) and high endurance (106) were achievedin the vertical configuration. Furthermore, InAs was incorporated as the GAA MOSFET selector channel material toleverage the beneficial transport properties of III-V materials desirable for supply voltage scaling. Finally, an approach wasdeveloped wherein InAs is used as the selector channel as well as the RRAM electrode by carefully tuning the InAs nativeoxides. This thesis also presents low-frequency noise characterization of the RRAM cell as well as the MOSFET to furtherunderstand the semiconductor/oxide interface. The vertical 1T1R cell developed in this thesis enables the implementationof Boolean logic operations using a single vertical nanowire while reducing the footprint by 51x when compared to itstraditional CMOS counterpart.