Sökning: "On-chip power supply."

Visar resultat 1 - 5 av 27 avhandlingar innehållade orden On-chip power supply..

1. 1. Performance and Energy Efficient Network-on-Chip Architectures

   Författare :Sriram Vangal; Atila Alvandpour; Wim Dehaene; Linköpings universitet; []
   Nyckelord :TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Chips; MOS transistors; Network-on-Chip NoC ; process technology; FPMAC; Electrical engineering; Elektroteknik;

   Sammanfattning : The scaling of MOS transistors into the nanometer regime opens the possibility for creating large Network-on-Chip (NoC) architectures containing hundreds of integrated processing elements with on-chip communication. NoC architectures, with structured on-chip networks are emerging as a scalable and modular solution to global communications within large systems-on-chip. LÄS MER

3. 2. Towards an on-chip power supply: Integration of micro energy harvesting and storage techniques for wireless sensor networks

   Författare :Agin Vyas; Chalmers tekniska högskola; []
   Nyckelord :TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Microsuperca- pacitor; On-chip power supply.; Piezoelectric energy harvester; CMOS compatible; MEMS;

   Sammanfattning : The lifetime of a power supply in a sensor node of a wireless sensor network is the decisive factor in the longevity of the system. Traditional Li-ion batteries cannot fulfill the demands of sensor networks that require a long operational duration. LÄS MER

4. 3. Performance and Energy Efficient Building Blocks for Network-on-Chip Architectures

   Författare :Sriram R. Vangal; Atila Alvandpour; Viktor Öwall; Linköpings universitet; []
   Nyckelord :NATURVETENSKAP; NATURAL SCIENCES; Network-on-Chip Architectures; floating-point units; tiled-architectures; crossbar routers; multi-processor interconnection; Computer engineering; Datorteknik;

   Sammanfattning : The ever shrinking size of the MOS transistors brings the promise of scalable Network-on-Chip (NoC) architectures containing hundreds of processing elements with on-chip communication, all integrated into a single die. Such a computational fabric will provide high levels of performance in an energy efficient manner. LÄS MER

5. 4. Core Switching Noise for On-Chip 3D Power Distribution Networks

   Författare :Waqar Ahmad; Hannu Tenhunnen; Atila Alvandpour; KTH; []
   Nyckelord :TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY;

   Sammanfattning : Reducing the interconnect size with each technology node and increasing speed with each generation increases IR-drop and Ldi/dt noise. In addition to this, the drive for more integration increases the average current requirement for modern ULSI design. LÄS MER

7. 5. Accurate Leakage-Conscious Architecture-Level Power Estimation for SRAM-based Memory Structures

   Författare :Minh Quang Do; Chalmers tekniska högskola; []
   Nyckelord :TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; SRAM Power Modeling; Deep Submicron; Power-Performance Estimation Tool; VLSI; Power Estimation; DSP Architecture; CMOS; Cache Power Modeling;

   Sammanfattning : Following Moore’s Law, technology scaling will continue providing integration capacityof billions of transistors for IC industry. As transistors keep shrinking in size, leakagepower dissipation dramatically increases and gradually becomes a first-class design constraint. LÄS MER