DSP algorithms and architectures for telecommunication

Sammanfattning: Techniques for providing users with high quality, high capacity digital transmission links has been in the research focus the last years. Both academia and industry try to come up with methods that can provide the consumers with high capacity transmission links at low price. Utilizing the twisted-pair copper wires that exist in almost every home for wideband data transmission is one of the most promising technologies for providing wideband communication capacity to the consumer.In this thesis we present algorithms and architectures suitable for the signal processing needed in the Asymmetrical Digital Subscriber Line (ADSL) and the Very High Speed Digital Subscriber Line (VDSL) standards. The FFT is one of the key blocks in both the ADSL and the VDSL standard. In this thesis we present an implementation of an FFT processor for these applications. The implementation was made adopting a new design methodology suitable for programmable signal processors that are optimized towards one or a few algorithms. The design methodology is presented, and an improved version where a tool for converting a combined instruction and algorithm description to a dedicated, programmable DSP processor is shown.In many applications as for instance video streaming the required channel capacity far exceeds what is possible today. Data must in those applications be compressed using various techniques that reduces the required channel capacity down to a feasible level. In this thesis architectures for image and video decompression is presented.Keeping the cost of ADSL and VDSL equipment low puts requirements on using low cost technologies. One way, proposed in this thesis, is to accept errors in the A/D and D/A converters and correct these errors utilizing digital signal processing, and a known application. Methods for cancellation of errors found in time interleaved A/D converters are proposed.