Sökning: "On-Chip Interconnect"

Visar resultat 1 - 5 av 24 avhandlingar innehållade orden On-Chip Interconnect.

1. 1. DDRNoC: Dual Data-Rate Network-on-Chip

   Författare :Ahsen Ejaz; Chalmers tekniska högskola; []
   Nyckelord :NATURVETENSKAP; NATURAL SCIENCES; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Network-on-Chip; On-Chip Interconnect; Dual Data-Rate; Multiprocessor System-on-Chip; Chip Multiprocessors; System-on-Chip;

   Sammanfattning : Networks-on-Chip (NoCs) are becoming increasing important for the performance of modern multi-core system-on-chip. For various on-chip networks with virtual channel (VC) ow control, the slow control logic (VC and switch allocation logic) of the NoC routers limits the NoC clock period while their datapath (switch and link) possesses signifcant slack. LÄS MER

3. 2. Dual Data Rate Network-on-Chip Architectures

   Författare :Ahsen Ejaz; Chalmers tekniska högskola; []
   Nyckelord :NATURVETENSKAP; NATURAL SCIENCES; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Dual Data-Rate; Network-on-Chip; System-on-Chip; On-Chip Interconnect; Chip Multiprocessors; Multiprocessor System-on-Chip;

   Sammanfattning : Networks-on-Chip (NoCs) are becoming increasing important for the performance of modern multi-core systems-on-chip. The performance of current NoCs is limited, among others, by two factors: their limited clock frequency and long router pipeline. The clock frequency of a network defines the limits of its saturation throughput. LÄS MER

4. 3. Efficient high-speed on-chip global interconnects

   Författare :Peter Caputa; Christer Svensson; Hartmut Grabinski; Linköpings universitet; []
   Nyckelord :TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Microelectronics; Global Interconnects; On-Chip Interconnects; Velocity-of-Light Delay; On-Chip Communication; Low-Latency; Transmission Lines; Electronics; Elektronik;

   Sammanfattning : The continuous miniaturization of integrated circuits has opened the path towards System-on-Chip realizations. Process shrinking into the nanometer regime improves transistor performancewhile the delay of global interconnects, connecting circuit blocks separated by a long distance, significantly increases. LÄS MER

5. 4. High-Performance Network-on-Chip Design for Many-Core Processors

   Författare :Boqian Wang; Zhonghai Lu; Kun-Chih Chen; KTH; []
   Nyckelord :NATURVETENSKAP; NATURAL SCIENCES; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Network-on-Chip; Chip Multi Many-core Processors; Multiprocessor System-on-Chip; High-Performance Computing; Cache Coherence; Virtual Channel Reservation; Admission Control; Artificial Neural Network; AXI4; Quality of Service; Network-on-Chip; Chip Multi Many-core Processors; Multiprocessor Sys-tem on a Chip; High-Performance Computing; Cache Coherence; Virtual Channel Reser-vation; Admission Control; Artificial Neural Network; AXI4; Quality of Servic; Informations- och kommunikationsteknik; Information and Communication Technology;

   Sammanfattning : With the development of on-chip manufacturing technologies and the requirements of high-performance computing, the core count is growing quickly in Chip Multi/Many-core Processors (CMPs) and Multiprocessor System-on-Chip (MPSoC) to support larger scale parallel execution. Network-on-Chip (NoC) has become the de facto solution for CMPs and MPSoCs in addressing the communication challenge. LÄS MER

7. 5. Modelling and Analysis of Interconnects for Deep Submicron Systems-on-Chip

   Författare :Dinesh Pamunuwa; KTH; []
   Nyckelord :delay and noise modelling in VLSI circuits; cross-talk; interconnect modelling; timing analysis; transfer function; on-chip bus; bandwidth maximization; throughput maximization; repeater insertion; wire optimization;

   Sammanfattning : The last few decades have been a very exciting period in thedevelopment of micro-electronics and brought us to the brink ofimplementing entire systems on a single chip, on a hithertounimagined scale. However an unforeseen challenge has croppedup in the form of managing wires, which have become the mainbottleneck in performance, masking the blinding speed of activedevices. LÄS MER