The transistor, with emphasis on its use for radio frequency telecommunication

Sammanfattning: This thesis is about transistors, integrated circuits and techniques to fabricate electronic devices in semiconductor materials. The most important application area for the transistors studied in the thesis is radio frequency telecommunication. The last decade has seen tremendous progress and expansion in the wireless telecommunication field, and greater efforts than ever are spent on improving and understanding semiconductor devices, especially their high-speed properties. The subjects treated in the thesis reflect today's industrial oriented research and development activities in this area, but the thesis also commemorates the inventention of the bipolar transistor 50 years ago by reviewing the early developments of the transistor and the integrated circuit.As integrated MOSFET dimensions are reduced, contact and interconnection parasitics tend to become more important and will ultimately limit overall circuit performance. In the polycide configuration the polycrystalline silicon used as gate material is shunted by a silicide layer to reduce RC time constants and resistive voltage drops. The salicide method takes the polycide idea a few steps further by selectively forming self-aligned silicide on exposed gate and source/ drain areas.In paper 1, the polycide configuration is extended for reducing the two major constraints inherent to the salicide method. A refined process scheme is described and experimentally verified. This allows simultaneous use of mutually different silicides on gate electrode and source/ drain areas and reduces the risk of silicide shorts. The process scheme will extend the process window, allow independent optimization of gate area and source/ drain area silicides and allow for a greater selection of materials, smoother topography and optimization of mechanical properties. The proposed scheme will also prevent short-circuits, "bridging", between parallel polysilicon lines.CMOS, bipolar and BiCMOS devices can be fabricated on thin silicon-on-insulator (SOI) materials using only slightly modified process flows and a standard silicon process line. SOI may extend the useful limit of high-frequency microwave devices in silicon, because the devices can be operated at higher frequencies, at lower supply voltage, and be very cost-effective, factors important for handheld telecommunication applications.In paper 2, a potential process problem when utilizing SOI-SIMOX materials for CMOS structures is investigated. High-dose BF2 and As implantations were studied at different energies and at elevated substrate temperature to investigate the degree of amorphization during source/ drain formation. High sheet resistance caused by grain boundaries and dislocations are expected on SIMOX even after a hightemperature activation. XTEM, electrical measurements and simulations were used to evaluate annealing during implantation to prevent amorphisation. The paper shows that with a proper tailoring of the implant conditions, it is possible to fabricate devices which may not need any additional silicide processing of source/drain areas, as 100 Ohms/square sheet resistivity of n+ and p+ areas may fulfil the requirements for a one micron technology and beyond.Silicon MOS-technology is the dominant IC technology for high-density low-cost circuits. Scaling the CMOS properties to attain higher densities of integration has led to the realization that the frequency of operation for single devices could be scaled up into the gigahertz domain at channel lengths around one micron and less. If a conventional CMOS process could also be used for high-frequency power applications, the devices will be simple to fabricate, have a high yield and thus a low price. Parameters like breakdown voltage, on-resistance, input/ output capacitances and layouts have to be optimized for this application.The objective of paper 3 and 4 is to study a possible realization of an integratable device for low voltage power amplification at gigahertz frequencies and its potential for use in UHF integrated circuits using conventional NMOS/CMOS technology. In paper 3, results from the first design approach, fabrication, characterization and power performance are presented, while in paper 4, an improved power MOSFET using an industry standard 1.3 um MOS technology is described. Devices were able to deliver up to 11 dB power gain at moderate power levels (20 dBm), and maximum saturated output power was estimated to 250-300 mW for the largest studied device. The devices in these papers were demonstrators Using the NMOS part of a CMOS fabrication technology but the results can be translated to BiCMOS or CMOS-SOI technology to achieve power gain at ultra-high frequencies in state-of-the-art IC technology.The bipolar RF power transistors are among the oldest silicon devices and have dominated the RF powerarea since beginning of the sixties. For cellular base stations, high-voltage bipolar transistors are almost exclusively used, and can deliver great performance up to and beyond 2 GHz with good stability, availability and price. In paper 5, an introduction to this area is given.In many areas in microelectronics, CAD tools have evolved considerably during the last decade. For RF power transistors, simulation methods still only offer limited help for amplifier design because these transistors represent maybe the toughest case for modeling of packaged devices. Model accuracy of the active device is the major limitation. Another equally important modeling problem, which has received considerably less attention, is the internal matching and the package.In paper 6, 3D electromagnetic simulations and SPICE are used to model the effects of wire geometry, internal matching and package on the small signal characteristics of an RF power transistor. A method for extracting the actual 3D properties of the bond wires and the package using SEM photos is presented. The geometry data is then used as illput to the electromagnetic simulators. Measured transistor data is compared with simulated data and the importance of the contributing elements and the coupling effects in the bondwire geometry are investigated.GaAIAs/GaAs heterojunction bipolar transistors (HBT:s) are among the most mature of a new generation of III-V semiconductor transistors that rely on heterojunctions for their operation. These devices offer potential advantages in microwave and high-speed applications over silicon homojunction devices.The objective of paper 7 is to study the feasibility of GaAIAs/GaAs HBTs as power output transistors for the same application as treated in paper 5 and 6. DC and small-signal HF characterization showed that the fabricated device fulfilled the device parameter goals, but power characterization at full supply voltage of 25 V failed because all devices blew up already at 20-22 V. The ballasting was increased, but with similar results. The explanation of the blown devices is most likely the dimension of the emitter, causing current crowding and nonuniform temperature distributions, which is further pronounced because of the high supply voltage and the GaAs material. The observed problems may severely limit the use of these devices for this and similar applications. The study shows a new technology with potentially superior performance, which when the actual device is realized, encounters unforeseen effects and processing limitations that hinders the unmediated use of the technology. It reveals how much work that has to be put into a new technology to reach similar or better performance than established technologies.