On Impact and Tolerance of Data Errors with Varied Duration in Microprocessors
Sammanfattning: The evolution of high-performance and low-cost microprocessors has led to their almost pervasive usage in embedded systems such as automotive electronics, smart gadgets, communication devices, etc. These mass-market products, when deployed in safety-critical systems, require safe services albeit at low recurring costs. Moreover, as these systems often operate in harsh environments, faults will occur during system operation, and thus, must be handled safely, i.e., tolerated.
This thesis investigates the efficiency of adding software-implemented fault tolerance techniques to commercial off-the-shelf (COTS) microprocessors. Specifically, the following problems are addressed:- Which faults need to be tolerated considering the architecture, implementation and operational environments for COTS processors?
- Which software-implemented fault-tolerance techniques are effective and efficient to use?
- How can the efficiencies of such designs be evaluated?
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