Sökning: "SRAM"

Visar resultat 1 - 5 av 11 avhandlingar innehållade ordet SRAM.

1. 1. Low Power Techniques for Fast CMOS Buffer Memories

   Författare :Jonas Alowersson; Institutionen för elektro- och informationsteknik; []
   Nyckelord :TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Systems engineering; low-power; throughput; buffer memory; CMOS; SRAM; computer technology; Data- och systemvetenskap;

   Sammanfattning : The thesis deals with circuit-level aspects of CMOS buffer SRAMs where the data throughput rate is a more important metric than access time or storage capacity. One aspect is the increased write cycle related power consumption that is the consequence of a high write ratio combined with a long word-length. LÄS MER

3. 2. Ultra-low Power Design Approaches in Memories and Assist Techniques

   Författare :Babak Mohammadi; Integrerade elektroniksystem; []
   Nyckelord :TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Memory; SRAM; assist technique; charge pump; ULP; ULV;

   Sammanfattning : The need for more functionality and higher performance has increased the number of transistors to billions in current processors. A high number of transistors on the same chip area increases the power density, which in turn heats up the devices and lowers the life time of batteries. LÄS MER

4. 3. Ultra-low Voltage Embedded Memories – Design Aspects and a Biomedical Use-case

   Författare :Oskar Andersson; Institutionen för elektro- och informationsteknik; []
   Nyckelord :TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; SRAM; CMOS; ultra-low voltage; ultra-low power; subthreshold; standard-cell based memories; atrial fibrillation; SRAM; CMOS; ultra-low voltage; ultra-low power; subthreshold; standard-cell based memories; atrial fibrillation;

   Sammanfattning : As the Internet of Things (IoT) era emerges the need for ultra-low power (ULP) devices is becoming more eminent. A research-proven approach to achieve ULP consumption is to aggressively lower the supply voltage (VDD) below or in the vicinity of the transistor threshold voltage (Vth) and operate the transistors in the subthreshold (sub-Vth) region. LÄS MER

5. 4. Accurate Leakage-Conscious Architecture-Level Power Estimation for SRAM-based Memory Structures

   Författare :Minh Quang Do; Chalmers tekniska högskola; []
   Nyckelord :TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; SRAM Power Modeling; Deep Submicron; Power-Performance Estimation Tool; VLSI; Power Estimation; DSP Architecture; CMOS; Cache Power Modeling;

   Sammanfattning : Following Moore’s Law, technology scaling will continue providing integration capacityof billions of transistors for IC industry. As transistors keep shrinking in size, leakagepower dissipation dramatically increases and gradually becomes a first-class design constraint. LÄS MER

7. 5. Single event upsets: measurements and modelling of proton- and neutron-induced errors in a 28 nm SRAM-based FPGA

   Författare :Markus Preston; Per-Erik Tegnér; Samuel Silverstein; Pawel Marciniewski; Andreas Heinz; Stockholms universitet; []
   Nyckelord :NATURVETENSKAP; NATURAL SCIENCES; Single event upset; FPGA; radiation damage; Monte Carlo simulation; PANDA; fysik; Physics;

   Sammanfattning : Single event upsets are radiation-induced errors affecting electronic devices, which can cause corruption of processed data. The electromagnetic calorimeter of the PANDA experiment — a hadron-physics experiment currently under development — will employ Xilinx Kintex-7 field-programmable gate arrays (FPGAs) in its readout electronics. LÄS MER