Charge Sampling Circuits and A/D Converters - Theory and Experiments

Detta är en avhandling från Department of Electroscience

Sammanfattning: The analysis of general charge sampling technique is presented in this thesis. Charge sampling integrates input current instead of tracking input voltage to realize high speed and low voltage sampling. The analysis focuses on the performance of general charge sampling circuits for signal capture. The theoretical analysis here can be applied not only for the weak signal capture, but also for the normal signal sampling. Based on a general charge sampling model, the transfer function, the noise performance and the clock jitter tolerance are analyzed and compared to conventional voltage sampling. The results provide a theoretical basis for the charge sampling circuit design. The extended work for an accurate sample-and-hold circuit model with a finite sampling duration is also presented. The results provide a better theoretical basis for understanding and designing a sample-and-hold circuit with finite tracking time, especially when considering the RF sampling (or subsampling) and kT/C noise. A CMOS 6-switch charge sampler is developed based on the charge sampling principle. With dummy capacitors operating alternatively in positive and negative branches, the resetting phase is embedded in the charging phase. The speed of the sampling is improved. A 500 MS/s charge sampling circuit was implemented in a 0.25 $mu$m CMOS process and measured. The dynamic range reaches 42 dB within the 250 MHz bandwidth. The power consumption is about 5 mW. Based on the principle of charge sampling, a novel charging FIR filters was suggested and implemented. The proposed FIR filter functions by summing the weighted current signal on a passive capacitor. First, the input signal is weighted by a resistor ladder, whose resistance is decided by the impulse response of the FIR filter. A linear transconductor then converts the weighted voltage to current and charges the capacitor linearly. The hardware cost is not proportional to the tap number in the proposed FIR filter. Two 32-tap filter prototypes were implemented in the AMS 0.35 $mu$m CMOS process. For the first filter, the measured sideband attenuation reaches -60 dB. The group delay is lower than 11 ns. The power consumption is about 35 mW under 3.3 V supply voltage. For the second one, the measured sideband attenuation is about -40 dB. The group delay is about 50 ns. The power consumption is about 7 mW under 2 V supply voltage. A differential difference comparator (DDC) is proposed for A/D conversion. The proposed DDC provides easy linear voltage subtraction and comparison functions via current operation. Since there are no feedback loops, the speed of the analog signal subtraction is inherently faster when being used in an analog-to-digital converter. Based the DDC, a CMOS ping-pang mode 200 MS/s 8 bit 2-step subranging A/D converter was implemented in the AMS 0.35 $mu$m CMOS process. Because of mismatch, the measured DNL for one branch is about 1.5 LSB and INL is about 2.2 LSB at 100 MS/s. The measured spurious free dynamic range at 100 MS/s (one branch) is 51 dB with 50 kHz sine input, while 39.2 dB at 200 MS/s (two branches) with 600 kHz signal input. The power consumption is 170 mW at 200 MS/s. Some other results on the A/D converters, such as an 80 dB sigma-delta modulator and a programmable A/D converter, are also included in the thesis. These works focus on the feasibility and flexibility study of the sigma-delta and pipelined A/D converters.

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