Studies on the Design and Implementation of Digital Filters

Sammanfattning: In this dissertation an efficient approach to design and implement fixed-function, high-speed recursive digital filters is presented. For a recursive algorithm there is an upper bound on the sample frequency of the corresponding implementation. A maximally fast implementation is an implementation with a sample frequency that is equal to this bound. The maximal sample frequency is determined by the ratio between the number of delay elements and the operation latency in the most time-critical recursive loop(s).We show how maximally fast implementations are obtained using a cyclic scheduling formulation that includes several sample periods. This formulation allows a simple isomorphic mapping of the arithmetic operations to a resourceoptimal hardware structure. The presented implementations are based on bit-serial arithmetic, but digit-serial and bit-parallel arithmetic are also feasible.The cyclic scheduling fonnulation can also be used to design shared-memory architectures with processing elements that are multiplexed to execute the operations. Two different wave digital filters are presented that have been implemented using the proposed design approach.We propose several numerically equivalent transformations that may yield algorithms with reduced iteration period bounds. These transformations are used on a lower level of abstraction, i.e., the arithmetic level, but they affect the critical loops of the algorithms. Further, we define several new latency models for the arithmetic operations with different amounts of pipelining and discuss their effect on the maximal sample frequency.A number of digital filters have been implemented to demonstrate that an increase in sample rate often can be achieved by the use of an appropriate logic style, pipelining of the arithmetic operations, and numerically equivalent transformations.An important advantage of this approach is that the excess speed achieved by a maximally fast implementation can be converted into reduced power consumption by operating a CMOS implementation with a reduced power supply voltage.