Sökning: "thread-level parallelism"
Visar resultat 1 - 5 av 6 avhandlingar innehållade orden thread-level parallelism.
1. Techniques to Reduce Thread-Level Speculation Overhead
Sammanfattning : The traditional single-core processors are being replaced by chip multiprocessors (CMPs) where several processor cores are integrated on a single chip. While this is beneficial for multithreaded applications and multiprogrammed workloads, CMPs do not provide performance improvements for single-threaded applications. LÄS MER
2. Improving Execution Efficiency by Targeting Redundancy and Parallelism
Sammanfattning : .... LÄS MER
3. SiLago: Enabling System Level Automation Methodology to Design Custom High-Performance Computing Platforms : Toward Next Generation Hardware Synthesis Methodologies
Sammanfattning : .... LÄS MER
4. Code Generation and Global Optimization Techniques for a Reconfigurable PRAM-NUMA Multicore Architecture
Sammanfattning : In this thesis we describe techniques for code generation and global optimization for a PRAM-NUMA multicore architecture. We specifically focus on the REPLICA architecture which is a family massively multithreaded very long instruction word (VLIW) chip multiprocessors with chained functional units that has a reconfigurable emulated shared on-chip memory. LÄS MER
5. Strategies to Reduce Energy and Resources in Chip Multiprocessor Systems
Sammanfattning : A new architectural style known as chip multiprocessor (CMP) has recently emerged, where two or more processor cores are manufactured on the same die. This architectural style comes with many promises such as high performance for applications with much thread-level parallelism (TLP) and shorter design times due to its modularized design. LÄS MER