Sökning: "baseband processor"

Visar resultat 1 - 5 av 15 avhandlingar innehållade orden baseband processor.

  1. 1. Design of Programmable Baseband Processors

    Författare :Eric Tell; Dake Liu; Béatrice Philibert; Linköpings universitet; []
    Nyckelord :NATURVETENSKAP; NATURAL SCIENCES; programmable; baseband; application specific; processor; architecture; instruction set; acceleration; software defined radio SDR ; digital signal processing DSP ; Computer engineering; Datorteknik;

    Sammanfattning : The world of wireless communications is under constant change. Radio standards evolve and new standards emerge. More and more functionality is put into wireless terminals. E. LÄS MER

  3. 2. Design of programmable multi-standard baseband processors

    Författare :Anders Nilsson; Dake Liu; Gerhard Fettweis; Linköpings universitet; []
    Nyckelord :NATURVETENSKAP; NATURAL SCIENCES; DSP; baseband processor; ASIP; Computer engineering; Datorteknik;

    Sammanfattning : Efficient programmable baseband processors are important to enable true multi-standard radio platforms as convergence of mobile communication devices and systems requires multi-standard processing devices. The processors do not only need the capability to handle differences in a single standard, often there is a great need to cover several completely different modulation methods such as OFDM and CDMA with the same processing device. LÄS MER

  4. 3. Efficient implementation of stream applications on processor arrays

    Författare :Jerker Bengtsson; Högskolan i Halmstad; []
    Nyckelord :NATURVETENSKAP; NATURAL SCIENCES; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Parallel processing; reconfigurable architectures; stream processing; baseband; Computer engineering; Datorteknik;

    Sammanfattning : This thesis concludes work conducted on exploring the usage of parallel and reconfigurable processor architectures in industrial high-performance embedded systems. This kind of systems has by tradition been built using a mix of digital signal processors and custom made hardware. LÄS MER

  5. 4. Dynamically Reconfigurable Architectures for Real-time Baseband Processing

    Författare :Chenxin Zhang; Institutionen för elektro- och informationsteknik; []
    Nyckelord :TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Reconfigurable Computing; Coarse-Grained Architecture; Dynamic Reconfiguration; SIMD; VLIW; ASIP; Vector Processor; Baseband Processing; OFDM; MIMO; Channel Estimation; Symbol Detection.;

    Sammanfattning : Motivated by challenges from today's fast-evolving wireless communication standards and soaring silicon design cost, it is important to design a flexible hardware platform that can be dynamically reconfigured to adapt to current operating scenarios, provide seamless handover between different communication networks, and extend the longevity of advanced systems. Moreover, increasingly sophisticated baseband processing algorithms pose stringent requirements of real-time processing for hardware implementations, especially for power-budget limited mobile terminals. LÄS MER

  7. 5. Baseband Processing for 5G and Beyond: Algorithms, VLSI Architectures, and Co-design

    Författare :Mojtaba Mahdavi; Institutionen för elektro- och informationsteknik; []
    Nyckelord :TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; VLSI Implementation; Hardware architectures; ASIC implementation; FPGA implementation; CMOS Technology; Baseband Processing; Massive MIMO; 5G New Radio; Beyond 5G; Co-Design; FFT processor; OFDM modulation; wireless communications; Massive MIMO Detection; Angular domain processing; Zero forcing; Systolic array; Non-linear detector; Channel Sparsity; Channel compression; Linear detector; Channel coding; Spatial coupling; Turbo-like codes; Spatially coupled serially concatenated codes; Threshold analysis; Decoder architecture; BCJR algorithm; MAP algorithm; Coupling memory; Window decoding; Complexity analysis; Performance Evaluation; Throughput; Decoding Latency; Silicon area; Design tradeoffs; Interleaver architecture; Memory requirements; Matrix multiplication; Channel state information CSI ; Cholesky decomposition; Tanner graph; Trellis codes; Convolutional encoder; Code design; Puncturing; Reordering circuit; wireless communication system; digital electronic;

    Sammanfattning : In recent years the number of connected devices and the demand for high data-rates have been significantly increased. This enormous growth is more pronounced by the introduction of the Internet of things (IoT) in which several devices are interconnected to exchange data for various applications like smart homes and smart cities. LÄS MER