Visar resultat 1 - 5 av 57 avhandlingar innehållade ordet System-on-chip.
Sammanfattning : There are several challenges that have to be considered in order to reduce the cost of System-on-Chip (SoC) testing, such as test application time, chip area overhead due to hardware introduced to enhance the testing, and the price of the test equipment. In this thesis the test application time and the test infrastructure hardware overhead of multiple-core SoCs are considered and two different problems are addressed. LÄS MER
2. Reconfigurable and Wideband Receiver Components for System-on-Chip Millimetre-Wave Radiometer Front-Ends
Sammanfattning : This thesis presents solutions and studies related to the design of reconfigurable and wideband receiver circuits for system-on-chip (SoC) radiometer front-ends within the millimetre-wave (mm-wave) range. Whereas many of today’s mm-wave front-ends are bulky and costly due to having discrete RF components, single-chip receiver modules could potentially result in a wider use for emerging applications such as wireless communication, short range radar and passive imaging security sensors if realised with adequate performances and at a lower cost. LÄS MER
Sammanfattning : The semiconductor technology has enabled the fabrication of integrated circuits (ICs), which may include billions of transistors and can contain all necessary electronic circuitry for a complete system, so-called System-on-Chip (SOC). In order to handle design complexity and to meet short time-to-market requirements, it is increasingly common to make use of a modular design approach where an SOC is composed of pre-designed and pre-verified blocks of logic, called cores. LÄS MER
Sammanfattning : Due to the increasing NRE costs of recent ASICs, the use of FPGAs is expected to continue to increase. While the first FPGAs were limited devices useful mainly for glue logic, todays FPGAs are highly capable devices used in many different application areas including telecommunication, multimedia, medical, and automotive. LÄS MER
Sammanfattning : Networks-on-Chip (NoCs) are becoming increasing important for the performance of modern multi-core system-on-chip. For various on-chip networks with virtual channel (VC) ow control, the slow control logic (VC and switch allocation logic) of the NoC routers limits the NoC clock period while their datapath (switch and link) possesses signifcant slack. LÄS MER