Sökning: "Parallel Memory Protocols"

Visar resultat 1 - 5 av 8 avhandlingar innehållade orden Parallel Memory Protocols.

  1. 1. Adaptable Hardware Transactional Memory Protocols

    Författare :Anurag Negi; Chalmers tekniska högskola; []
    Nyckelord :NATURVETENSKAP; NATURAL SCIENCES; multicore; transactional memory; parallel programming;

    Sammanfattning : Transactional Memory (TM) is an important programming paradigm that can help alleviate difficulties associated with concurrent programming. Single-threaded performance can no longer be expected to scale as it did in the past. Programmers, therefore, must seriously consider concurrent algorithms as viable alternatives. LÄS MER

  3. 2. Towards Large-Capacity and Cost-Effective Main Memories

    Författare :Dmitry Knyaginin; Chalmers tekniska högskola; []
    Nyckelord :NATURVETENSKAP; NATURAL SCIENCES; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Fairness; Energy Efficiency; Hybrid Main Memory; Performance; Design-Space Exploration; Parallel Memory Protocols; Large-Capacity Local Memory; Hardware-Based Hybrid Memory Management; Cost-Effectiveness;

    Sammanfattning : Large, multi-terabyte main memories per processor socket are instrumental to address the continuously growing performance demands of domains like high-performance computing, databases, and big data. It is an important objective to design large-capacity main memories in a way that maximizes their cost-effectiveness and at the same time minimizes performance losses caused by cost-effective tradeoffs. LÄS MER

  4. 3. Towards Accurate and Resource-Efficient Cache Coherence Prediction

    Författare :Jim Nilsson; Chalmers tekniska högskola; []
    Nyckelord :NATURVETENSKAP; NATURAL SCIENCES; cache coherence protocols; performance evaluation; computer architecture; memory systems; shared memory multiprocessors;

    Sammanfattning : The increasing speed gap between processor microarchitectures and memory technologies can potentially slow down the historical performance growth of computer systems. Parallel applicationns on shared memory multiprocessors that experience cache misses due to communication are extra susceptible to this speed difference. LÄS MER

  5. 4. Architecture Support and Scalability Analysis of Memory Consistency Models in Network-on-Chip based Systems

    Författare :Abdul Naeem; Axel Jantsch; Zhonghai Lu; Jari Nurmi; KTH; []
    Nyckelord :TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Memory consistency; Protected release consistency; Distributed shared memory; Network-on-Chip; Scalability;

    Sammanfattning : The shared memory systems should support parallelization at the computation (multi-core), communication (Network-on-Chip, NoC) and memory architecture levels to exploit the potential performance benefits. These parallel systems supporting shared memory abstraction both in the general purpose and application specific domains are confronting the critical issue of memory consistency. LÄS MER

  7. 5. Evaluation of design alternatives for a directory-based cache coherence protocol in shared-memory multiprocessors

    Författare :Håkan Grahn; Blekinge Tekniska Högskola; []
    Nyckelord :NATURVETENSKAP; NATURAL SCIENCES;

    Sammanfattning : In shared-memory multiprocessors, caches are attached to the processors in order to reduce the memory access latency. To keep the memory consistent, a cache coherence protocol is needed. LÄS MER