Sökning: "Last level cache"
Visar resultat 6 - 10 av 19 avhandlingar innehållade orden Last level cache.
6. Toward Next-generation Data Centers : Principles of Software-Defined “Hardware” Infrastructures and Resource Disaggregation
Sammanfattning : The cloud is evolving due to additional demands introduced by new technological advancements and the wide movement toward digitalization. Therefore, next-generation data centers (DCs) and clouds are expected (and need) to become cheaper, more efficient, and capable of offering more predictable services. LÄS MER
7. A Slowdown Prediction Method to Improve Memory Aware Scheduling
Sammanfattning : Scientific and technological advances in the area of integrated circuits have allowed the performance of microprocessors to grow exponentially since the late 1960's. However, the imbalance between processor and memory bus capacity has increased in recent years. LÄS MER
8. Adaptive Resource Management Techniques for High Performance Multi-Core Architectures
Sammanfattning : Reducing the average memory access time is crucial for improving the performance of applications executing on multi-core architectures. With workload consolidation this becomes increasingly challenging due to shared resource contention. Previous works has proposed techniques for partitioning of shared resources (e.g. LÄS MER
9. Secure System Virtualization : End-to-End Verification of Memory Isolation
Sammanfattning : Over the last years, security-kernels have played a promising role in reshaping the landscape of platform security on embedded devices. Security-kernels, such as separation kernels, enable constructing high-assurance mixed-criticality execution platforms on a small TCB, which enforces isolation between components. LÄS MER
10. High Performance Hybrid Memory Systems with 3D-stacked DRAM
Sammanfattning : The bandwidth of traditional DRAM is pin limited and so does not scale well with the increasing demand of data intensive workloads limiting performance. 3D-stacked DRAM can alleviate this problem providing substantially higher bandwidth to a processor chip. LÄS MER