Sökning: "Instruction Scheduling"
Visar resultat 16 - 20 av 20 avhandlingar innehållade orden Instruction Scheduling.
16. Architectures and Compilation Techniques for a Data-Driven Processor Array
Sammanfattning : This thesis presents two processor array architectures and a program transformation technique, which are aimed at efficient exploitation of fine-grain parallelism. The class of architectures considered are fine-grain processor arrays with a data-driven execution model. LÄS MER
17. Securing concurrent programs with dynamic information-flow control
Sammanfattning : The work presented in this thesis focusses on dealing with timingcovert channels in dynamic information-flow control systems,particularly for the LIO library in Haskell.Timing channels are dangerous in the presence ofconcurrency. LÄS MER
18. Hiding and Reducing Memory Latency : Energy-Efficient Pipeline and Memory System Techniques
Sammanfattning : Memory accesses in modern processors are both far slower and vastly more energy-expensive than the actual computations. To improve performance, processors spend a significant amount of energy and resources trying to hide and reduce the memory latency. LÄS MER
19. Laying Tiles Ornamentally: An approach to structuring container traversals
Sammanfattning : Having hardware more capable of parallel execution means that more program scheduling decisions have to be taken to utilize that hardware efficiently. To this end, compilers implement coarse-grained loop transformations in addition to traditionally used fine-grained instruction reordering. LÄS MER
20. High-Level Synthesis for SiLago : Advances in Optimization of High-Level Synthesis Tool and Neural Network Algorithms
Sammanfattning : Embedded hardware designs and their automation improve energy and engineering efficiency. However, these two goals are often contradictory. The attempts to improve energy efficiency often come at the cost of engineering efficiency and vice-versa. High-level synthesis (HLS) is a good example of this challenge. LÄS MER