Sökning: "Instruction Scheduling"
Visar resultat 11 - 15 av 20 avhandlingar innehållade orden Instruction Scheduling.
11. Techniques to Tighten the Upper Bound on the ExecutionTime of Task-based Parallel Applications
Sammanfattning : To use multiprocessors in hard real-time systems, schedulability analysis is needed to provide formally proven guarantees for the timing behavior of the system. Programming models for parallel applications, such as OpenMP, use pragmas to specify parts of the application as parallel tasks, for example, a function or a body of a loop. LÄS MER
12. Static instruction scheduling for high performance on energy-efficient processors
Sammanfattning : New trends such as the internet-of-things and smart homes push the demands for energy-efficiency. Choosing energy-efficient hardware, however, often comes as a trade-off to high-performance. LÄS MER
13. The Impact of Application and Architecture Properties on Real-Time Multiprocessor Scheduling
Sammanfattning : Guaranteeing the temporal correctness of a real-time system is a very challenging problem since application and architecture properties may be hard to model accurately. For example, modern computer architectures are typically equipped with mechanisms, such as cache memories and instruction pipelines, whose behavior are by nature stochastic. LÄS MER
14. Integrated Code Generation
Sammanfattning : Code generation in a compiler is commonly divided into several phases: instruction selection, scheduling, register allocation, spill code generation, and, in the case of clustered architectures, cluster assignment. These phases are interdependent; for instance, a decision in the instruction selection phase affects how an operation can be scheduled. LÄS MER
15. A dynamic programming approach to optimal retargetable code generation for irregular architectures
Sammanfattning : In this thesis we address the problem of optimal code generation for irregular architectures such as Digital Signal Processors (DSPs). Code generation consists mainly of three tasks: instruction selection, instruction scheduling and register allocation. LÄS MER