Sökning: "Christoph Kessler"
Visar resultat 6 - 10 av 16 avhandlingar innehållade orden Christoph Kessler.
6. Integrated Code Generation
Sammanfattning : Code generation in a compiler is commonly divided into several phases: instruction selection, scheduling, register allocation, spill code generation, and, in the case of clustered architectures, cluster assignment. These phases are interdependent; for instance, a decision in the instruction selection phase affects how an operation can be scheduled. LÄS MER
7. Integrated Software Pipelining
Sammanfattning : In this thesis we address the problem of integrated software pipelining for clustered VLIW architectures. The phases that are integrated and solved as one combined problem are: cluster assignment, instruction selection, scheduling, register allocation and spilling. LÄS MER
8. Designing a Modern Skeleton Programming Framework for Parallel and Heterogeneous Systems
Sammanfattning : Today's society is increasingly software-driven and dependent on powerful computer technology. Therefore it is important that advancements in the low-level processor hardware are made available for exploitation by a growing number of programmers of differing skill level. LÄS MER
9. Pattern-based Programming Abstractions for Heterogeneous Parallel Computing
Sammanfattning : Contemporary computer architectures utilize wide multi-core processors, accelerators such as GPUs, and clustering of individual computers into complex large-scale systems. These hardware trends are prevalent across computers of all sizes, from the largest supercomputers down to the smallest mobile phones. LÄS MER
10. Code Generation and Global Optimization Techniques for a Reconfigurable PRAM-NUMA Multicore Architecture
Sammanfattning : In this thesis we describe techniques for code generation and global optimization for a PRAM-NUMA multicore architecture. We specifically focus on the REPLICA architecture which is a family massively multithreaded very long instruction word (VLIW) chip multiprocessors with chained functional units that has a reconfigurable emulated shared on-chip memory. LÄS MER