Sökning: "Cache performance"

Visar resultat 21 - 25 av 92 avhandlingar innehållade orden Cache performance.

  1. 21. Adaptive Microarchitectural Optimizations to Improve Performance and Security of Multi-Core Architectures

    Författare :Nadja Holtryd; Chalmers tekniska högskola; []
    Nyckelord :TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Multi-Core Architectures; Bandwidth Partitioning; Prefetch Throttling; Cache Partitioning; Microarchitectural Optimizations; Side-channel Attacks;

    Sammanfattning : With the current technological barriers, microarchitectural optimizations are increasingly important to ensure performance scalability of computing systems. The shift to multi-core architectures increases the demands on the memory system, and amplifies the role of microarchitectural optimizations in performance improvement. LÄS MER

  3. 22. Efficient methods for application performance analysis

    Författare :David Eklöv; Erik Hagersten; Uppsala universitet; []
    Nyckelord :NATURVETENSKAP; NATURAL SCIENCES; Datavetenskap; Computer Science;

    Sammanfattning : To reduce latency and increase bandwidth to memory, modern microprocessors are designed with deep memory hierarchies including several levels of caches. For such microprocessors, the service time for fetching data from off-chip memory is about two orders of magnitude longer than fetching data from the level-one cache. LÄS MER

  4. 23. Leveraging Existing Microarchitectural Structures to Improve First-Level Caching Efficiency

    Författare :Ricardo Alves; David Black-Schaffer; Stefanos Kaxiras; Mattan Erez; Uppsala universitet; []
    Nyckelord :NATURVETENSKAP; NATURAL SCIENCES; Energy Efficient Caching; Memory Architecture; Single Thread Performance; First-Level Caching; Out-of-Order Pipelines; Instruction Scheduling; Filter-Cache; Way-Prediction; Value-Prediction; Register-Sharing.;

    Sammanfattning : Low-latency data access is essential for performance. To achieve this, processors use fast first-level caches combined with out-of-order execution, to decrease and hide memory access latency respectively. LÄS MER

  5. 24. Realizing High Performance NFV Service Chains

    Författare :Georgios P. Katsikas; Dejan Kostic; Gerald Maguire Jr.; Fabian Schneider; KTH; []
    Nyckelord :TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; NFV; service chains; profiler; scheduling; multiplexing; synthesis; line-rate; 40 Gbps; NFV; service kedjor; profilering; planläggningsstrategier; syntetiserade; 40 Gbps; Informations- och kommunikationsteknik; Information and Communication Technology; Computer Science; Datalogi;

    Sammanfattning : Network functions (NFs) hold a key role in networks, offering in-network services, such as enhanced performance, policy enforcement, and security. Traditionally, NFs have been implemented in specialized, thus expensive hardware. LÄS MER

  7. 25. A Slowdown Prediction Method to Improve Memory Aware Scheduling

    Författare :Andreas de Blanche; Stefan Christiernin; Thomas Lundqvist; Per Stenström; Nectarios Koziris; Högskolan Väst; []
    Nyckelord :TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; SAMHÄLLSVETENSKAP; SOCIAL SCIENCES; Multi-core processor; slowdown aware scheduling; memory bandwidth; resource contention; last level cache; co-scheduling; performance evaluation; Datateknik; Computer engineering;

    Sammanfattning : Scientific and technological advances in the area of integrated circuits have allowed the performance of microprocessors to grow exponentially since the late 1960's. However, the imbalance between processor and memory bus capacity has increased in recent years. LÄS MER