Schedulability and Memory Interference Analysis of Multicore Preemptive Real-time Systems

Sammanfattning: Today's embedded systems demand increasing computingpower to accommodate the ever-growing software functionality.Automotive and avionic systems aim to leverage thehigh performance capabilities of multicore platforms, but arefaced with challenges with respect to temporal predictability.Multicore designers have achieved much progress onimprovement of memory-dependent performance in cachingsystems and shared memories in general. However, havingapplications running simultaneously and requesting the accessto the shared memories concurrently leads to interference.The performance unpredictability resulting from interferenceat any shared memory level may lead to violationof the timing properties in safety-critical real-time systems.In this paper, we introduce a formal analysis framework forthe schedulability and memory interference of multicore systemswith shared caches and DRAM. We build a multicoresystem model with a ne grained application behavior givenin terms of periodic preemptible tasks, described with explicitread and write access numbers for shared caches andDRAM. We also provide a method to analyze and recommendcandidates for task-to-core reallocation with the goalto nd schedulable congurations if a given system is notschedulable. Our model-based framework is realized usingUppaal and has been used to analyze a case study

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