Power Estimation and Low Power CMOS Circuit Techniques
Sammanfattning: The increasing power consumption due to the high integration rate of VLSI digital CMOS circuits has become a major concern. Many important design issues and parameters are strongly dependent on the power dissipation and the accuracy of its estimated value during the design exploration. Among these issues we identify particularly the operation time per battery pack, the computational capacity and performance of the mobile electronic products, as well as more general aspects such as circuit reliability, cost for packaging and power supplies. In this thesis, some issues on power estimation and development of low-power circuit techniques, aimed for medium and high speed operations, are addressed.The complex impact of Miller capacitance on power and performance of digital CMOS circuits is investigated. Significant enhancements in characterization and modeling of the Miller effects compared to the existing conclusions, which are based on simplified rules, are achieved.A novel estimation technique for the relatively involved average short-circuit power consumption has been developed. Compared to the existing, time-consuming technique, the proposed technique provides a fast estimation with a reasonable accuracy, and has a potential to be used for real measurement.A significant portion of the total power consumption in VLSI circuits is due to the capacitance of the interconnections, however, estimating the interconnect length and its RC property at early stages in a large-scale top-down design flow is a hard task. Existing, simplified interconnection length estimation techniques are unacceptably inaccurate and unable to give a useful feedback during the design verification and simulation.A new design-sensitive interconnection length estimation technique and a corresponding algorithm has been developed. The technique has the unique quality to estimate the length of each interconnection separately, and therefore detects and localizes most of the potentially long interconnects. The result of the estimation can directly be used to add the important RC properties of the interconnects to the power estimators or circuit simulators, consequently yielding a significant increase in estimation accuracy.An investigation on generic low-power circuit techniques aimed for main-stream design styles has been made and various suggestions are proposed. The result has later been used to adapt the design of cell libraries to low power requirements.High fan-in dynamic gates can result in lower power consumption, fewer logic levels and very compact layout. Two major disadvantages, which reduce the practical use of such wide gates, are the relatively long propagation delay and the large leakage currents, which are due to the increasing subthreshold current in today's and future submicron devices. For speeding up the wide gates, new and simple sensing elements are proposed, which results in faster gates and lower power consumption compared to the alternative solutions. The issues related to large subthreshold leakage currents is also addressed and a leakage-tolerant multi-phase keeper circuit is presented. The new keeper holds the dynamic output of the wide domino gates statically, with a greater driving strength than that in the conventional solution. Furthermore, an increase in robustness is achieved without any significant delay penalty.Large capacitive loads resulting from long on-chip interconnects and the corresponding driver-receiver circuits can consume a significant portion of the total power consumption of a CMOS chip. A low-power, high-speed and robust driver-receiver circuit is proposed. The new bus architecture utilizes a precharge-to-low interconnect and a fast and simple level converter as receiver, which together reduce the power consumption up to 70% below that of a conventional precharged bus architecture without any delay penalty.
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