Testability analysis and improvement in high-level synthesis systems

Sammanfattning:

With the level of integration existing today in VLSI technology, the cost of testing a digital circuit has become a very significant part of a product. This cost mainly comes from the test pattern generation (ATPG) for a design and the test execution for each product. Therefore it is worthwhile to detect parts of a design which are difficult for ATPG and test execution, and improve these parts before using ATPG and testing.

There are existing methods of improving the testability of a design, such as the scan path technique. However, due to the high cost of introducing scan registers for all registers in a design and the delay caused by long scan paths, these approaches are not very efficient. In this thesis, we propose a method which only selects parts of a design to be transformed based on the testability analysis. For this purpose, wedefine a testability measurement which is able to predict the costs to be spent during the whole test procedure.evaluate the result of the testability measurement, and based on this evaluation develop some strategies to identify difficult-to-test parts in a design.create a class of testability improvement transformations and apply them to the difficult-to-test parts identified.recalculate testability for the design with part of it transformed.

These procedures are repeated until design criteria are satisfied. The implementation result conforms to our direct observation. For test examples discussed in the thesis, we find the best improvement of testability within the other design constraint.