Low Voltage CMOS Radio Receiver Front-End Design

Sammanfattning: The mass production of integrated circuits for digital electronics has made CMOS technology the most frequently used IC process today. Thanks to the large production volume, CMOS has increasingly become the most cost efficient technology of choice, and the fast development of small, high speed CMOS devices has made the technology feasible for many RF applications. However, as the transistor feature size continues to shrink, the maximum supply voltage decreases as well, and it becomes important to fully utilized the available dynamic range. New circuit architectures must therefore be developed in order not to deteriorate RF performance or increase power consumption. The scope of this thesis has been to investigate circuit topologies for low voltage CMOS receiver front-ends, where the developments of the passive mixer represent the main contribution. The general introduction provides a brief overview of receiver architectures, CMOS technology, low voltage front-end design, linearity aspects, and generation of quadrature signals on chip. Brief introductions to the included papers are placed in their context where the purpose of the research becomes clearer. Paper I presents a 1 Volt front-end aimed for the Bluetooth standard where maximum dynamic range is achieved. Paper II and III describe developments of the passive mixer where linearity improvement and quadrature functionality are addressed. The papers present fabricated and measured circuits in a standard 0.25um CMOS technology. Paper IV deals with large signal nonlinearity of the passive mixer and makes use of an effective analysis method based on phase shifting. The final paper studies quadrature generation on chip by using an active polyphase network.