Applications of decision diagrams for low power synthesis

Sammanfattning: Power consumption is an important design constraint for circuits used in portable devices. In this thesis an analytic approach to minimize the power dissipation of Binary Decision Diagram (BDD) mapped digital circuits is presented. We also present a re-synthesis algorithm that collapses standard cell gates into custom complex static CMOS gates for lower power dissipation. The first approach combines logic minimization, low power optimization and mapping to a Pass Transistor Logic (PTL) multiplexor circuit. This method utilizes statistical properties for the input signals to reduce the estimated power dissipation. Experimental results for the PTL based synthesis algorithm on MCNC (combinational) and ISCAS89 (sequential) benchmarks show significant reductions of the estimated power dissipation. The ISCAS89 results show an average reduction of 40 percent and up to 90 percent on individual benchmarks. The synthesis is guided by estimation of the switching activity, which can be used to estimate the power dissipation. Three different switching activity estimation algorithms are presented. The most advanced method is also compared to an exact method. The results from the tests shows that the third method will give a good estimation in a much shorter computation time than the exact method. The re-synthesis algorithm works on an existing standard cell netlist by composing basic gates into complex gates. The larger and fewer gates will result in lower power dissipation, which will be further enhanced by process scaling. Tests show that the re-synthesis algorithm reduces the power dissipation on an average by 15 percent and up to 35 percent on individual benchmarks compared to a standard cell netlist. A technique for computing the switching activity of synchronous Finite State Machine (FSM) implementations including the influence of temporal correlation among the next state signals is described. The approach is based upon the computation that a FSM is in a given state which, in turn, is used to compute the conditional probability that a next state bit changes given its present state value. All computations are performed using Decision Diagram (DD) data structures. As an application of this method, the next state activity information is utilized for low power optimization in the synthesis process.