VLSI Architectures and Arithmetic Operations with Application to the Fermat Number Transform

Sammanfattning: The properties of arithmetic operations in Fermat integer quotient rings 2m+1, where m = 2t, are investigated. The arithmetic operations considered are mainly those involved in the computation of the Fermat number transform. We consider some ways of representing the binary coded integers in such rings and investigate VLSI architectures for arithmetic operations, with respect to the different element representations. The VLSI architectures are mutually compared with respect to area (A) and time (T) complexity and area-time performance (AT2). The VLSI model chosen is a linears witch-level RC model.In the polar representation, the nonzero elements of a field are represented by the powers of a primitive element of the field. In the thesis we particularly investigate the properties of arithmetic operations and their corresponding VLSI architectureswith respect to the polar representation of the elements of Fermat prime fields. Somenew results regarding the applicability of the Fermat number transform when usingthe polar representation are also presented.