Multicarrier Faster-than-Nyquist Signaling Transceivers: From Theory to Practice

Sammanfattning: Popular Abstract in English In the past decade, mobile wireless communication have had a tremendous impact on the way people perceive and use mobile devices, most popularly the mobile phone. Apart from making phone calls, they are capable of being cameras to take pictures and videos, able to browse the Internet, do video calling and much more just like an yesteryear computer. The wireless medium is the air through which information is transmitted using electromagnetic waves and is similar to a radio being tuned to particular frequency to listen to a station broadcasting a program. However, mobile wireless communication is much more complicated due to the two-way nature as well as the variety of information that is being transmitted. Further, the number of frequencies, referred to as bandwidth, required is a lot more for a mobile device. There has been a tremendous improvement and demand for bandwidth resources in the recent past and is continuing to grow. Hence efficient use of bandwidth resources has become a key parameter in the design and realization of wireless communication systems. Faster-than-Nyquist (FTN) signaling is one such technique that achieves bandwidth efficiency by making better use of the available bandwidth resources. Along with the inclusion of a lot of features into the mobile devices they still need to be compact and be capable of operating on batteries. This implies that the underlying hardware realizing the wireless functionality need to be small and consume less power. This thesis addresses the challenges and design trade offs arising during the hardware realization of transmitter and receiver for faster-than-Nyquist signaling. The FTN system has been evaluated for its achievable performance compared to the processing overhead in both the transmitter and receiver. Coexistence with existing and upcoming wireless systems has been considered so that they can be seamlessly integrated. An efficient hardware architecture that reuses the underlying blocks for different purposes has been designed, implemented and verified on an ASIC that uses a state-of-the-art chip fabrication technology.