Digital Phase Locked Loops for Radio Frequency Synthesis

Sammanfattning: The demands for an ever higher data rate and a more varied functionality at minimal cost and power consumption have been the driving force behind most innovations in wireless communication systems. Intensive efforts have been made to develop Radio Frequency (RF) Integrated Circuits (ICs) and systems using low-cost Complementary Metal Oxide Semiconductor (CMOS) processes. In radio transceivers for wireless systems, the commonly used frequency synthesizer based on a Phase Locked Loop (PLL) is a crucial building block. In fact, the frequency synthesizer is responsible for the generation of high-purity RF signals utilized to shift up and down in frequency the information content of the transmission, and, as such, determines the performance of the whole transceiver to a large extent, while it is responsible for a large portion of the power consumed and the area occupied by the transceiver.A state-of-the-art PLL must meet stringent requirements on signal purity, while dissipating increasingly lower power to lengthen battery lifetime and being capable of operating at the very low supply voltages required by modern CMOS processes. Furthermore, such a PLL should occupy a small area and coexist with very complex digital systems, which are responsible for the generation of extensive switching noise.With the extraordinary pace of CMOS technology scaling and the attending increase in integration density, conventional analog designs are giving way to digital counterparts, which much better exploit the new silicon ecosystems. The foremost example of this momentous trend is probably the PLL, where the Digital Phase Locked Loop (DPLL) can exploit all the advantages, in terms ofprogrammability, reconfigurability, and adoption of advanced adaptive digital algorithms for the correction of PLL non-idealities, that are beyond the reach of the analog PLL.In this dissertation, several IC design techniques are demonstrated, which improve the DPLL in terms of both overall architecture and individual subblocks. One DPLL has been designed and thoroughly simulated, while one Digitally Controlled Oscillator (DCO) and another DPLL have been designed, simulated, fabricated, and tested, obtaining excellent measured performance