Micro- and Millimeter Wave CMOS Beamforming Receivers

Sammanfattning: The available bandwidth in wireless communication systems, such as the 802.11 family, is very limited. Together with the ever increasing data traffic, this causes problems. New possibilities are, however, available thanks to wide license-free bandwidth allocated at higher frequencies. Increased available bandwidth enables higher data rates in future radio systems that will be capable of Giga-bit/s communication applications. This creates new possibilities like transferring very large amounts of data in a short time between computers and their peripheral devices, wireless HD-video to and from smart phones, eliminating cables between video-source and video-projector, etc. The available bandwidth is, however, located at much higher frequencies than in current WiFi systems for private usage, that is, 2.4 and 5.8 GHz. This brings new challenges from both a system as well as a circuit perspective. Wave propagation at 60 GHz differs from 2.4 GHz and 5.8 GHz. The most substantial differences are the propagation loss and the small aperture of the millimeter wave antennas, which limit the possible communication distance between receiver and transmitter. Adopting beamforming transmitters focuses the transmitted energy into the desired direction, increasing the energy available at the receiver. Correspondingly, adopting beamforming receivers also increases the received signal energy by increasing the antenna gain. Beamforming is, therefore, a key technique in increasing communication distance. This thesis investigates CMOS beamforming receiver circuits and architectures for microwave and millimeter wave radio communication. Traditionally, III-V semiconductor technologies have been used for millimeter wave applications. Today, however, as the gate length of silicon CMOS devices has been continuously reduced thanks to advancements in IC fabrication, their maximum frequency of operation is also sufficient for millimeter waves. Several circuits have been designed and measured to validate new ideas. Among these circuits, five are included in the thesis. A chip with two fully-integrated phase-locked loops with digital phase control for beamforming receivers is presented in paper I, and an injection locked voltage controlled oscillator with phase control is presented paper II. A two channel 24 GHz receiver with beamforming implemented in the analog baseband is proposed in paper III, and a high-speed low-power inductor-less 24 GHz CML frequency divider is presented in paper IV, including an on-chip VCO for test purposes. Finally, in paper V a 60 GHz receiver with a digitally controllable phase using a phase-locked loop, based on the results of paper I, is presented. The circuit achieves a state-of-the-art phase control accuracy with a measured phase step error of less than 1 degree.

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