Vertical III-V/High-k Nanowire MOS Capacitors and Transistors

Sammanfattning: The emerging nanowire technology in recent years has attracted an increasing interest for high-speed, low-power electronics due to the possibility of a gate-all-around (GAA) geometry enabling aggressive gate length scaling, together with the ease in incorporating high-mobility narrow band gap III-V semiconductors such as InAs on Si substrates. These benefits make vertical nanowire transistors an attractive alternative to the planar devices. However, huge challenges are also encountered. Apart from the large parasitics associated with the device layout, vertical III-V/high-k nanowire MOSFETs so far are also suffering from a less efficient gate control partially due to the defect states existing in the MOS gate stack. Besides the narrow band gap InAs may result in impact-ionization and band-to-band tunneling at high drain voltages, influencing both the power efficiency and speed of modern integrated circuits (ICs).

In this thesis, results on planar InAs/high-k MOS gate stacks investigated in detail using both the capacitance-voltage (C-V) and the x-ray photoelectron spectroscopy (XPS) techniques are first presented (Paper I and II). The origin of the specific trap state energy distribution is clarified and compared to the well studied InGaAs and GaAs materials. The results highlight the benefit of using InAs, with optimized high-k deposition strategies, as the n-MOSFET channel.

The second focus of the thesis is the improvement of vertical GAA nanowire MOS gate stacks (Paper III and IV). By developing the fabrication scheme and design, conventional C-V technique is successfully applied to extract detailed trap state distributions. A low interface trap state density (Dit) below 10E12 eV-1cm-2 near the MOS semiconductor conduction band edge is achieved. Furthermore, RF C-V measurements, together with the development of a complete small signal equivalent circuit model, for vertical GAA nanowire MOS systems are also presented for the first time, which enables characterizations of border trap density, interface trap density, channel resistivity and quality factor of the nanowire MOSFETs simultaneously.

The third focus is the development of a device structure to reduce detrimental impact-ionization and band-to-band tunneling due to the narrow band gap of InAs (Paper V and VI). An asymmetric InAs/InGaAs vertical nanowire MOSFET with a large band gap drain region is proposed, taking advantage of the efficient strain relaxation of nanowire epitaxial growth. Control of the InGaAs nanowire composition has been successfully demonstrated.

Finally, a vertical integration scheme was developed in the thesis, where track-and-hold circuits, consisting of a MOSFET in series with a metal-insulator-metal capacitor, were successfully fabricated along vertical InAs nanowires (Paper VII).