A/D Conversion for Sensor Systems
Sammanfattning: Today, an important field for circuit design research is advanced mixed mode CMOS circuits for the most varying purposes. By designing these for implementation in basic and cheap digital technologies, building blocks for advanced systems are achieved. Two examples are described in this thesis; a smart CMOS camera and AID conversion for carrier frequency signals.The CMOS camera is developed using the Near-Sensor Image Processing concept, NSIP. The concept has previously been presented. It is based on a focal plane processor with one processor in each pixel. The two main properties, that make the concept successful are that the light intensity is converted to a time value, which means that we can process single bit information with maintained grey scale information, and an asynchronous propagation net, which can mark connected areas in the image. The contribution of this thesis is the implementation of an NSIP camera. A low power circuit technique with self clocked instructions is developed for this SIMD machine. The processor architecture based on NAND operations is developed for minimizing the area. The light sensor read-out circuitry is developed for low power and small area. A patent is pending for this part. The result is a 32 x 32 pixels test circuit with possibilities to extend to 128 x 128 pixels in existing technologies. The operation speed can be up to 100 MHz. The power consumption is 400 [email protected] 10 MHz (in 128 x 128 pixels). The asynchronous mark operation can process 4 · 106 frames/s.The carrier frequency ADC is based on a patent describing a novel technique for finding Inphase and Quadrature signals from an intermediate frequency, fIF, signal. It has earlier been tested in a multi chip system. This thesis shows an implementation of this method in a single CMOS chip, by using Multiple Sampling Single Conversion, MSSC. A test circuit that operates on fIF= 30 MHz and gives 10 bits 2 MHz output was fabricated. The experiences from this circuit initiated studies about metastability and about high speed architectures for SA-ADCs. A model, which compares metastability with quantization noise, is presented. Design rules for achieving a desired SNR can be specified from this model. One high speed architecture was developed. The SA-ADC uses binary search among reference levels for finding the correct representation. The new architecture is based on a Reference Pre-Select, RPS, scheme, which minimizes the time between two comparisons. The result is 200 MHz 10 bits simulated performance. Partly working circuits have been fabricated.
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