# Resitive FET Mixers

Sammanfattning: This thesis presents theory, device models and circuits related to resistive FET mixers:

• A wave analysis for resistive mixers
The analysis gives an intuitive estimate of resistive mixer performance when most parameters are unknown. It is based on the assumption that all mixing terms generated in the mixer are terminated with the same impedance. An expression for the conversion efficiency is therefore simple to derive in time domain. For HFETs and MESFETs, the wave analysis is extended to incorporate the effect of the local oscillator power level. The analysis methods are successfully verified by measurements.
• A symmetrical HFET/MESFET nonlinear model
The nonlinear FET model reflects the intrinsic symmetry of microwave HFETs and MESFETs. The model is successfully verified by intermodulation measurements on mixers and amplifiers.
• Single device balanced resistive FET mixers
Two types of single device balanced resistive HEMT mixers are presented. The mixers utilize the inherent symmetry of the FET to achieve balanced operation. The first type has a balanced, and the other a single ended, extraction of the intermediate frequency. Both types are successfully verified at 20 GHz.
• A FET transceiver suitable for FMCW radars
The FET transceiver uses the same device for output power generation as for down-conversion of the received signal. The FET operates simultaneously as an amplifier and as a resistive mixer. It, thereby, avoids the problems associated with the separation of the transmitted and received signals which are closely spaced in frequency. The circuit is, empirically, shown to be insensitive to DC-bias variations. We also derive a method to optimize the output power simultaneously with the mixer conversion efficiency.
• A resistive FET frequency multiplier
The operation of the multiplier is analogous to that of the resistive FET mixer. The wave analysis mentioned above is used to deduce the optimum way of operating the FET as well as estimating the conversion efficiency of a multiply-by-n circuit. The theoretical analysis is verified with two different 2 to 4 GHz multipliers. The verification shows good agreement between theory and measurements.

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