Silicon nanowire based devices for More than Moore Applications

Författare: Ganesh Jayakumar; Per-erik Hellström; Mikael Östling; Luca Selmi; Kth; []

Nyckelord: silicon nanowire; biosensor; CMOS; sequential integration; lab-on-chip; LOC; high-K; high-K integration on SiNW biosensor; ALD; fluid gate; back gate; SiNW; SiNW pixel matrix; FEOL; pattern transfer lithography; sidewall transfer lithography; STL; multi-target bio detection; BEOL; nanonets; silicon nanonets; SiNN-FET; SiNW-FET; CMOS integration of nanowires; CMOS integration of nanonets; monolithic 3D integration of nanowires; above-IC integration of nanowires; DNA detection using SiNW; SiNW biosensor; dry environment DNA detection; DNA hybridization detection using SiNW; SiNW functionalization; SiNW silanization; SiNW grafting; FEOL integration of SiNW; BEOL integration of SiNW; sequential multiplexed biodetection; biodetection efficiency of SiNW; front end of line integration of SiNW; back end of line integration of SiNW; SiNW dry environment functionalization; APTES cross-linker; accessing SiNW test site; fluorescence microscopy of SiNW; geometry of SiNW; SiNW biosensor variability; top-down fabrication of SiNW; bottom-up fabrication of SiNW; VLS method; ams foundry CMOS process; adding functionality in BEOL process; sensor integration in BEOL process; hafnium oxide; HfO2; aluminium oxide; Al2O3; TiN backgate; Nickel source drain; ISFET; ion sensitive field effect transistor; Overcoming Nernst limit of detection using SiNW; SiNW sub-threshold region operation; ASIC; SOC; SiGe selective epitaxy; epitaxial growth of SiNW; epitaxial growth of nanowires; epitaxial growth of nanonets; nickel silicide contacts; salicide process; high yield SiNW fabrication; high volume SiNW fabrication; silicon ribbon; SiRi pixel; SiRi biosensor; SiRi DNA detection; monolithic 3D integration of nanonets; above-IC integration of nanonets; impact of back gate voltage on silicon nanowire; impact of back gate voltage on SiNW; FDSOI; fully depleted silicon on insulator technology; metal backgate; wafer scale integration of SiNW; wafer scale integration of nanonets; impact of backgate voltage on CMOS inverter circuit; frequency divider; D flip-flop; Informations- och kommunikationsteknik; Information and Communication Technology;

Sammanfattning: Silicon nanowires (SiNW) are in the spotlight for a few years in the research community as a good candidate for biosensing applications. This is attributed to their small dimensions in nanometer scale that offers high sensitivity, label-free detection and at the same time utilizing small amount of sample. While the recent research has concentrated predominantly on utilizing single or multiple SiNW for biosensing applications, very few attempts have been made to integrate SiNW with complementary-metal-oxide- semiconductor (CMOS) integration to arrive at a complete lab-on-chip (LOC) sensor. Further, the manufacturing methods reported thus far in the production of SiNW for biosensing applications have not fully exploited both the front-end-of-line (FEOL) as well as back-end-of-line (BEOL) methods in CMOS integration. Neither does the research community address CMOS integration based methods to realize multi and specific target detection that are important attributes for an ideal LOC biosensor.Integration of SiNW with CMOS circuitry will facilitate real time detection of the output signal and in addition provide a compact small sized sensor that is fully portable operating at high speed. In order to avail the benefits of CMOS circuits and develop a large scale production friendly LOC sensor, the scheme of SiNW fabrication has to facilitate either the FEOL or BEOL CMOS integration schemes. This thesis work is focused on revealing a novel FEOL as well as BEOL scheme for integration of SiNW with CMOS circuitry. The major part of the FEOL research work is concentrated on developing a high volume SiNW manufacturing method that is suitable for industrial production. Likewise, in the BEOL scheme, predominant focus was to develop a wafer scale scheme to integrate network of nanowires (nanonets) with CMOS circuitry to manufacture a monolithic 3D above-IC LOC biosensor.In the FEOL scheme, the SiNWs are fabricated using a revised pattern transfer technique called sidewall transfer lithography (STL). The STL method is identified as one of the efficient methods of fabricating SiNW as it uses CMOS industry grade materials that is fully compatible with the FEOL fabrication scheme. Thanks to the usage of single lithography and controlled selective etching techniques used in the STL process, the line width and aspect ratio of the SiNW can be tailored to suit the requirements for DNA hybridization detection. A fabrication process flow matching standard CMOS process integration flows has been developed to integrate SiNW with HfO2 and TiN metal gate MOSFETS. An emphasis has been placed in the design of a novel pixel matrix based SiNW LOC sensor. Specific and multi-target detection has been kept as top priority in the design of the SiNW LOC sensor. The possibility to monitor the potential of the electrolyte during the detection process using a fluid gate has been accounted in this design. Furthermore, the SiNW pixel design eliminates the intricate microfluidics and eases access to the SiNW test site using a simple photolithography mask and RIE. The SiNW and MOSFETS demonstrate excellent electrical characteristics. For the very first time, the concept to access single as well as multiple array SiNW pixels using a transistor has been successfully demonstrated.In the BEOL scheme, the nanonets are fabricated using the bottom-up method and transferred onto a pre-fabricated CMOS wafer supplied by ams foundry. The connection between the nanonets lying above-IC and the underlying CMOS layer was established by employing a thin metal backgate electrode, backgate dielectric and metal source/drain contact pads. Many challenges in the BEOL scheme have been identified and overcome by incorporating efficient device architecture and careful selection of materials. To the first of its kind, a wafer scale process was developed to integrate nanonets with CMOS to form a monolithic 3D IC. The devices exhibit excellent electrical characteristics and lower leakage currents compared to standalone nanonet sensors fabricated on Si/SiN substrate. Further, the FEOL and BEOL integration schemes are compared and the various pro’s and con’s of both approaches for integration of SiNW with CMOS circuits to build a LOC biosensor are discussed in detail.Finally, dry environment DNA hybridization detection is demonstrated on the surface of thin HfO2 encapsulated SiNW sensors. Upon DNA hybridization, SiNW devices exhibit threshold voltage shift larger than the noise introduced by the exposition to saline solutions used for the bio-processes. More specifically, based on a statistical analysis, it is demonstrated that 85% of the tested devices were efficient for DNA hybridization detection. The estimated density of hybridized DNA was in the order of 1010 cm-2. These promising results of realizing a SiNW based lab-on-chip platform through the FEOL and BEOL monolithic integration of SiNW and CMOS circuitry further strengthen the profile of SiNW as a nano biosensor. Indeed, this is expected to pave the way for more than Moore applications of SiNW based devices and integrated circuits.

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