Design of large scale and high speed intergrated systems

Sammanfattning: For integrated systems, as the scale grows larger and the speed goes higher, designers face many challenges. The topics in this thesis are concentrated on five design issues in large scale and high speed integrated systems. These challenging issues have been met in designing an ATM chip with a total throughput of 80Gb/s in a 0.8μm BiCMOS technology.To achieve high speed in the IC, full-custom design has to been used. The drawback of full-custom design is the longer time and the higher cost of the design process. Efficient methods are required to shorten the design time and cost. A layout based schematic (LBS) method is addressed. In this method parasitic components, diodes and wires, are added automatically based on the topology of the circuit. Hence, designers do not need to draw layouts of all possible options. A good agreement between the results from LBS and real layout is obtained, therefore the design efficiency is improved.In an early system design phase, we need to predict the interconnection delay, power and area for getting a reasonable budget which should not cause any disaster in future system implementation. In a long wire driving, to reduce delay, power or area is also quite important. A simple and useful analytic solution is given to optimize long wire driving subject to the condition of given delay, power and area or their products. Comparison results show that a good accuracy of the analytic solution is reached in accordance with SPICE simulation.A multiphase digital clock/pattern generator is proposed for a large scale and high speed system where interference and noise are serious. This technique can be used to replace PLL frequency synthesizer when high speed multiphase clocks are available. The maximum time resolution is equal to half of the phase difference. A clock generator is designed with 8 clock phases at 622MHz obtained by dividing a 5 GHz clock, to generate a system clock at 622MHzx32/53=376MHz for the ATM switch.For level conversion from low swing to high high swing, or a long clock buffer chain, circuits are very sensitive to design mismatch. In high speed applications, this becomes serious when the number of the stages is very large. A perfect control of pulse width is needed for some applications. A pulse width control loop is presented for multistage clock buffers in large scale and high speed systems. Two identical charge pumps are used for creating reference and detecting width. The delay in a long clock buffer can cause instability in loop control. Stability analysis is given in order to keep the loop functioning correctly.The most significant contribution in this thesis is the implementations of mesochronous clocking by methods of self-tested self-synchronization (STSS). In mesochronous clocking, a serious problem is the metastability in data reading. To avoid it, STSS is presented. The concept of failure zone and failure angle is described, and based on this concept approaches to failure detection are expressed. Using failure detection, several solutions to self-synchronization are proposed. These solutions can be utilized for designing next generation silicon chips with massive parallel processing elements (PE) and heavy interconnections between them. It also is an answer for connecting different IP blocks from various vendors in large systems-on-chip. It is believed that this communication method will become very useful in designing a future microprocessor design, or high speed large scale parallel systems.