Sökning: "register file cache"

Hittade 4 avhandlingar innehållade orden register file cache.

  1. 1. Techniques to Cancel Execution Early to Improve Processor Efficiency

    Författare :Mafijul Islam; Chalmers tekniska högskola; []
    Nyckelord :NATURVETENSKAP; NATURAL SCIENCES; processor design; energy-efficiency; narrow-width cache; instruction reuse; zero-value cache; resource-efficient; narrow-width load; complexity-effective; small value locality; register file cache; frequent value locality; trivial instruction; silent load; high-performance; zero load;

    Sammanfattning : The evolution of computer systems to continuously improve execution efficiency has traditionally embraced various approaches across microprocessor generations. Unfortunately, contemporary processors still suffer from several inefficiencies although they offer an unprecedented level of computing capabilities. LÄS MER

  3. 2. An Automated and Controlled Numerical Precision Reduction Framework for GPUs

    Författare :Alexandra Angerd; Chalmers tekniska högskola; []
    Nyckelord :NATURVETENSKAP; NATURAL SCIENCES; NATURVETENSKAP; NATURAL SCIENCES; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Microarchitecture; Floating-Point Precision; Approximate Computing; Register File; GPU;

    Sammanfattning : Reducing the precision of floating-point values is an effective approach to achieve higher performance as well as higher energy-efficiency. This is especially true for GPUs, since many of its common tasks are inherently insensitive to precision-reduction. LÄS MER

  4. 3. Leveraging Existing Microarchitectural Structures to Improve First-Level Caching Efficiency

    Författare :Ricardo Alves; David Black-Schaffer; Stefanos Kaxiras; Mattan Erez; Uppsala universitet; []
    Nyckelord :NATURVETENSKAP; NATURAL SCIENCES; Energy Efficient Caching; Memory Architecture; Single Thread Performance; First-Level Caching; Out-of-Order Pipelines; Instruction Scheduling; Filter-Cache; Way-Prediction; Value-Prediction; Register-Sharing.;

    Sammanfattning : Low-latency data access is essential for performance. To achieve this, processors use fast first-level caches combined with out-of-order execution, to decrease and hide memory access latency respectively. LÄS MER

  5. 4. Hiding and Reducing Memory Latency : Energy-Efficient Pipeline and Memory System Techniques

    Författare :Andreas Sembrant; David Black-Schaffer; Erik Hagersten; David A. Wood; Uppsala universitet; []
    Nyckelord :TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; NATURVETENSKAP; NATURAL SCIENCES; Computer Science; Datavetenskap;

    Sammanfattning : Memory accesses in modern processors are both far slower and vastly more energy-expensive than the actual computations. To improve performance, processors spend a significant amount of energy and resources trying to hide and reduce the memory latency. LÄS MER