Studies on implementation of digital filters with high throughput and low power consumption

Sammanfattning: In this thesis we discuss design and implementation of frequency selective digital filters with high throughput and low power consumption. The thesis includes proposed arithmetic transformations of lattice wave digital filters that aim at increasing the throughput and reduce the power consumption of the filter implementation. The thesis also includes two case studies where digital filters with high throughput and low power consumption are required.A method for obtaining high throughput as well as reduced power consumption of digital filters is arithmetic transformation of the filter structure. In this thesis arithmetic transformations of first- and second-order Richards' allpass sections composed by symmetric two-port adaptors and implemented using carry-save arithmetic are proposed. Such filter sections can be used for implementation of lattice wave digital filters and bireciprocal lattice wave digital filters. The latter structures are efficient for implementation of interpolators and decimators by factors of two. The proposed transformations increase the throughput of the filter implementation. The increased throughput can be traded for reduced power consumption through power supply voltage scaling.In the thesis two typical applications for digital filters with high throughput and low power consumption are studied, a digital down converter for a multiple antenna radar system and a combined interpolation and decimation filter for oversampled ADCs and DACs in an OFDM system. For both these cases several different filter structures have been consideredand evaluated with respect to arithmetic complexity and throughput. The purpose with these evaluations were to find the most power efficient implementations.For the digital down converter, three different filter structures, combining FIR filters and wave digital filters, have been implemented in VHDL and mapped to a standard cell design using a cell library in a 0.18 μm CMOS process. For the combined interpolator and decimator, four different novel filter structures were considered. One of these structures was implemented using a standard cell library in a 0.35 μm CMOS process. The functionality of the implementation has been verified and the power consumption of the filter chip has been measured.